SystemVerilog Testbenches That Actually Catch Bugs

Most testbenches generate activity. Very few generate knowledge. This book is about the difference.

Through seventeen project-based chapters you build real verification environments from scratch: a synchronous FIFO, a UART monitor, an AXI-Stream scoreboard, an SPI master, a dual-clock CDC bridge, a pipelined multiplier with latency-aware checking, and a regression that runs unattended. Each chapter...